The present invention relates generally to electronic circuits used to generate clock signals and more specifically to phase-locked loops (PLLs) manufactured in deep-submicron integrated circuit (IC) technologies.
Phase-Locked Loops are circuits that produce an output clock signal whose phase can be locked to the phase of an input reference clock signal. Phase, in the context of a PLL, means a signal's frequency value integrated over a time period. Therefore, the phase of the signal equals the number of clock cycles during the time period. The ratio of the frequency of the output clock signal and the frequency of the reference clock signal can be a positive integer number, in which case the PLL is called an integer-N PLL or an “integer PLL”; or it can be a positive rational number, in which case the PLL is called a fractional-N PLL or a “fractional PLL”. Rational numbers are numbers that can be expressed as a ratio of two integers. In the context of this document, a fractional-N number is a positive rational number consisting of an integer part (obtained by rounding down to the nearest integer number) and a fractional part.
A PLL includes a controlled oscillator that produces the output clock signal. An analog PLL usually has an analog-controlled oscillator such as a voltage-controlled oscillator (VCO), and a digital PLL may have an analog-controlled oscillator or a digitally-controlled oscillator (DCO), which may include a digital-to-analog converter followed by an analog-controlled oscillator. A PLL locks the phase (and, as a result, frequency) of the output clock signal to the phase of the reference clock signal by measuring the accumulated number of output clock cycles and adjusting the controlled oscillator frequency when the measured number deviates from a required (or predicted) number, based on a frequency control word (FCW). The ratio of output clock cycles to reference clock cycles, measured over some duration, is called the PLL's multiplication factor. When a conventional PLL is in lock, its multiplication factor matches its FCW and its output frequency matches a target frequency defined as the reference clock frequency times the FCW.
Frequency-Locked Loops (FLLs) are circuits that produce an output clock signal whose frequency is locked to the frequency of an input reference clock signal. Compared to a PLL, an FLL lacks the integration or accumulation over time. A PLL's integration may occur anywhere in its loop, for example in feedback circuits, or in feedforward circuits such as a loop filter. Whereas a PLL in lock will lock both frequency and phase ratios in output and reference signals, an FLL may lock just the frequency ratio but not necessarily the phase ratio.
In an integer-N PLL, the spacing of possible output clock frequencies (also called the frequency resolution) typically equals the frequency of the reference clock signal, since the output clock frequency equals a positive integer number times the reference clock frequency. Increasing or decreasing the positive integer number by one will result in the output clock frequency increasing or decreasing by the reference frequency. A better output frequency resolution can be achieved by using a lower reference clock frequency. However, in practical PLLs this will often increase the jitter.
A fractional-N PLL can have a much better output clock frequency resolution without the need for a low reference clock frequency, as the ratio between the output clock and reference clock frequencies can be a positive rational number. An example of a fractional-N PLL is described in U.S. Pat. No. 8,994,423, entitled Phase-Locked Loop Apparatus and Method by Jenkins. The circuits described there provide very high accuracy and low jitter. However, new applications require ever higher speed, higher accuracy, a larger range, lower jitter, and lower power. To meet these requirements simultaneously, embodiments of the invention incorporate novel architectures and methods.